Field of the Invention
The present invention is related to semiconductor device manufacturing and more particularly to forming protrusions on an article, such as a semiconductor integrated circuit (IC) chip.
Background Description
Typical semiconductor integrated circuit (IC) chips have layers stacked such that layer features overlay one another to form individual devices and connect devices together. ICs are mass produced by forming an array of chips on a thin semiconductor wafer. Each array location is known as a die and each die may harbor a multilayered structure, such as an IC chip or a structure for test or alignment.
As transistor technologies have evolved, chip features and devices have gotten smaller and smaller and have minimum dimensions that typically are well below one micrometer (1 μm) or 1 micron. Smaller chip features and devices allow IC manufacturers to integrate more function in the same chip real estate. A typical IC can include billions of transistors wired together into circuits providing chip function. IC circuits may also include micro-machine structures such as micro-sensors or other micro-electro-mechanical systems (MEMS) structures. A typical MEMS structure, such as a cantilever and membrane formation, has been formed by stacking multiple layers of interlevel vias beneath a surface wiring structure and undercutting the surface wiring without damaging surrounding features.
The surface layer of each completed chip or die is typically populated by probable off-chip pads for connecting to chip power and input/output (I/O) signals. Packing more function on each die typically means providing more and more I/O signals for each die, on one (top), or for a three dimensional (3D) chip structure, both (top and bottom) sides. Each die has at least one surface pad for each I/O signal and a number of power (supply and ground) connection pads. Providing these I/O signals and supply as die are shrinking in size, therefore, drives more stringent off-chip I/O connection requirements, i.e., increasingly dense I/O pad arrays. On a typical state of the art IC wafer, for example, the surface layer of each die may be populated by several thousand connection pads. To achieve this requires ultra-fine pitch pads on very tight a pitch less than 50 microns (<50 μm).
Typically, each of these very densely packed chip pads may also be populated with a solder ball, most commonly lead (Pb) free solder, for connecting the chip to, or mounting it on, a single or multi chip module. The solder balls, e.g., controlled collapsible chip connections (C4s), are formed or bumped onto the pads, for example, for what is known as ball grid array (BGA) joining Any difficulty in forming these solder ball on a 2D chip surface at coarse pitch, e.g., 200 μm, is exacerbated for ultra-fine pitch arrays on both sides of a 3D chip or on a module surface.
Testing these tightly packed pads with or without solder balls requires very fine, delicate, tightly-packed test probes. Historically, what are known as cobra probes were used to probe down to 150 μm. Probing tightly-packed pads at 50 μm and below requires very precise probe tip geometry control and scalability. Achieving necessary probe tip precision for probing ultra-fine pitch pads has proven very difficult, and therefore, expensive.
Thus, there is a need for simplifying chip bumping for densely populated IC chip pads, for fabricating low cost probes for probing those ultra-fine pitch pads and bumps, and for simply forming MEMS structures without complicating manufacturing and without making process control more stringent.